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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:06:36 +0200 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:06:36 +0200 |
| commit | 114b643dd0125518c5f0b40959057dcf316f5007 (patch) | |
| tree | 0efd14eb04458078cc3e2256771586703fa0b854 /src/arch/x86/isa/microops | |
| parent | 47bcc5c7379c7de677996ba8bfcd826d93459c09 (diff) | |
| download | gem5-114b643dd0125518c5f0b40959057dcf316f5007.tar.xz | |
x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 6d4687830..d77e5f559 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1679,4 +1679,18 @@ let {{ break; } ''' + + class Wrxftw(WrRegOp): + def __init__(self, src1, **kwargs): + super(Wrxftw, self).__init__(src1, "InstRegIndex(NUM_INTREGS)", \ + **kwargs) + + code = ''' + FTW = X86ISA::convX87XTagsToTags(SrcReg1); + ''' + + class Rdxftw(RdRegOp): + code = ''' + DestReg = X86ISA::convX87TagsToXTags(FTW); + ''' }}; |