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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:19 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:19 -0600 |
| commit | 91b00d98a5973d47b831495f5c668bbb185c7a15 (patch) | |
| tree | d2108f83a8be89fdaeec5120c5f5ccb6744cdba1 /src/arch/x86/isa/microops | |
| parent | 7fdcfdf08b9d654fcf311b213bd729cb957f822c (diff) | |
| download | gem5-91b00d98a5973d47b831495f5c668bbb185c7a15.tar.xz | |
x86: implement fabs, fchs instructions
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index f6cbd2036..b9aceea09 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -331,4 +331,12 @@ let {{ else if(FpSrcReg1 == FpSrcReg2) ccFlagBits = ccFlagBits | ZFBit; ''' + + class absfp(FpUnaryOp): + code = 'FpDestReg = fabs(FpSrcReg1);' + flag_code = 'FSW &= (~CC1Bit);' + + class chsfp(FpUnaryOp): + code = 'FpDestReg = (-1) * (FpSrcReg1);' + flag_code = 'FSW &= (~CC1Bit);' }}; |