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author | Nilay Vaish <nilay@cs.wisc.edu> | 2011-11-03 22:52:21 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2011-11-03 22:52:21 -0500 |
commit | 582ea4d5431f9fa9edbeb16835b04171647ea18b (patch) | |
tree | a9a3ae50ff09f7791525cf8313d8afec67f9f3e3 /src/arch/x86/isa/microops | |
parent | fb5c095cd53f4f16e139d9e959c41e089ff79896 (diff) | |
download | gem5-582ea4d5431f9fa9edbeb16835b04171647ea18b.tar.xz |
x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
Diffstat (limited to 'src/arch/x86/isa/microops')
-rw-r--r-- | src/arch/x86/isa/microops/specop.isa | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 52420f175..5c242e2c9 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -1,4 +1,5 @@ // Copyright (c) 2007-2008 The Hewlett-Packard Development Company +// Copyright (c) 2011 Mark D. Hill and David A. Wood // All rights reserved. // // The license below extends only to copyright in the software and shall @@ -203,3 +204,55 @@ let {{ microopClasses["halt"] = Halt }}; + +def template MicroFenceOpDeclare {{ + class %(class_name)s : public X86ISA::X86MicroopBase + { + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint64_t setFlags); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFenceOpConstructor {{ + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, uint64_t setFlags) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + setFlags, %(op_class)s) + { + %(constructor)s; + } +}}; + +let {{ + class MfenceOp(X86Microop): + def __init__(self): + self.className = "Mfence" + self.mnemonic = "mfence" + self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)" + + def getAllocator(self, microFlags): + allocString = ''' + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s)) + ''' + allocator = allocString % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags) + self.instFlags} + return allocator + + microopClasses["mfence"] = MfenceOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase', + {"code" : ""}) + header_output += MicroFenceOpDeclare.subst(iop) + decoder_output += MicroFenceOpConstructor.subst(iop) + exec_output += BasicExecute.subst(iop) +}}; |