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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-04 23:22:08 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-04 23:22:08 -0700 |
| commit | b0b4038ee985bcd1d677f464d71812fb9827c9ce (patch) | |
| tree | 9c5b7664f132fe6300086ae4e69e7336a5cec00b /src/arch/x86/isa/microops | |
| parent | e1e7605213bf5dc5f469c0293fe4caf6f3d0ef92 (diff) | |
| download | gem5-b0b4038ee985bcd1d677f464d71812fb9827c9ce.tar.xz | |
X86: Fix a corner case where mul would overwrite an original register value it still needed.
--HG--
extra : convert_revision : 86ee0e2bf716d52c34ee731727d6366935f103ed
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index a0477dab7..e169b09d2 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -453,7 +453,7 @@ let {{ ''' class Mulel(FlagRegOp): - code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize)' + code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize);' class Muleh(FlagRegOp): code = ''' |