diff options
author | Gabe Black <gabeblack@google.com> | 2017-11-02 01:58:38 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2017-11-02 09:43:35 +0000 |
commit | 8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch) | |
tree | f791cd8adccee52d054f5a10b62948021a3d121b /src/arch/x86/isa/microops | |
parent | 97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff) | |
download | gem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz |
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/x86/isa/microops')
-rw-r--r-- | src/arch/x86/isa/microops/debug.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 21 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/limmop.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 4 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/seqop.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/specop.isa | 5 |
8 files changed, 19 insertions, 21 deletions
diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index b14202ac5..87e7879f1 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -84,7 +84,7 @@ def template MicroDebugDeclare {{ def template MicroDebugExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 6ba292977..5973c7d06 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -46,7 +46,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroFpOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 6dd2b6f6b..2f1c267a2 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -48,7 +48,7 @@ // LEA template def template MicroLeaExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -88,7 +88,7 @@ def template MicroLeaDeclare {{ // Load templates def template MicroLoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -118,7 +118,7 @@ def template MicroLoadExecute {{ }}; def template MicroLoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -137,9 +137,8 @@ def template MicroLoadInitiateAcc {{ }}; def template MicroLoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT * xc, - Trace::InstRecord * traceData) const + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc, + Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -162,7 +161,7 @@ def template MicroLoadCompleteAcc {{ // Store templates def template MicroStoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::execute(ExecContext * xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -190,7 +189,7 @@ def template MicroStoreExecute {{ }}; def template MicroStoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -214,7 +213,7 @@ def template MicroStoreInitiateAcc {{ def template MicroStoreCompleteAcc {{ Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const + ExecContext * xc, Trace::InstRecord * traceData) const { %(op_decl)s; %(op_rd)s; @@ -228,12 +227,12 @@ def template MicroStoreCompleteAcc {{ //This delcares the initiateAcc function in memory operations def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; //This declares the completeAcc function in memory operations def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template MicroLdStOpDeclare {{ diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index c002a1684..ac0438ae0 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -42,7 +42,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroLimmOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 63e22a23f..19bbc6392 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -29,7 +29,7 @@ // Authors: Gabe Black def template MediaOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dc5f0affe..2f8fc4dfc 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -42,7 +42,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroRegOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -73,7 +73,7 @@ def template MicroRegOpExecute {{ }}; def template MicroRegOpImmExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index 76766e055..601aa6775 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -68,7 +68,7 @@ def template SeqOpDeclare {{ }}; def template SeqOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 77c459097..2b1d8ba44 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -88,7 +88,7 @@ def template MicroFaultDeclare {{ }}; def template MicroFaultExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; @@ -104,8 +104,7 @@ def template MicroFaultExecute {{ output exec {{ Fault - MicroHalt::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord * traceData) const + MicroHalt::execute(ExecContext *xc, Trace::InstRecord * traceData) const { xc->tcBase()->suspend(); return NoFault; |