Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.

--HG--
extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f

4 files changed, 28 insertions, 22 deletions

diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 7fa4f0457..a066d4802 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -64,14 +64,14 @@ let {{
 //A class which is the base of all x86 micro ops. It provides a function to
 //set necessary flags appropriately.
 output header {{
-    class X86MicroOpBase : public X86StaticInst
+    class X86MicroopBase : public X86StaticInst
     {
       protected:
         const char * instMnem;
         uint8_t opSize;
         uint8_t addrSize;
 
-        X86MicroOpBase(ExtMachInst _machInst,
+        X86MicroopBase(ExtMachInst _machInst,
                 const char *mnem, const char *_instMnem,
                 bool isMicro, bool isDelayed,
                 bool isFirst, bool isLast,
@@ -79,10 +79,10 @@ output header {{
             X86StaticInst(mnem, _machInst, __opClass),
             instMnem(_instMnem)
         {
-            flags[IsMicroOp] = isMicro;
+            flags[IsMicroop] = isMicro;
             flags[IsDelayedCommit] = isDelayed;
-            flags[IsFirstMicroOp] = isFirst;
-            flags[IsLastMicroOp] = isLast;
+            flags[IsFirstMicroop] = isFirst;
+            flags[IsLastMicroop] = isLast;
         }
 
         std::string generateDisassembly(Addr pc,
@@ -108,15 +108,19 @@ let {{
         def __init__(self, name):
             self.name = name
 
+        # This converts a python bool into a C++ bool
+        def cppBool(self, val):
+            if val:
+                return "true"
+            else:
+                return "false"
+
         # This converts a list of python bools into
         # a comma seperated list of C++ bools.
         def microFlagsText(self, vals):
             text = ""
             for val in vals:
-                if val:
-                    text += ", true"
-                else:
-                    text += ", false"
+                text += ", %s" % self.cppBool(val)
             return text
 
         def getAllocator(self, mnemonic, *microFlags):
@@ -130,7 +134,7 @@ let {{
 //////////////////////////////////////////////////////////////////////////
 
 def template MicroLdStOpDeclare {{
-    class %(class_name)s : public X86MicroOpBase
+    class %(class_name)s : public X86MicroopBase
     {
       protected:
         const uint8_t scale;
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 5fce37126..a25d2b712 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -72,7 +72,7 @@ def template MicroLimmOpExecute {{
 }};
 
 def template MicroLimmOpDeclare {{
-    class %(class_name)s : public X86MicroOpBase
+    class %(class_name)s : public X86MicroopBase
     {
       protected:
         const RegIndex dest;
@@ -141,7 +141,7 @@ let {{
 
 let {{
     # Build up the all register version of this micro op
-    iop = InstObjParams("limm", "Limm", 'X86MicroOpBase',
+    iop = InstObjParams("limm", "Limm", 'X86MicroopBase',
             {"code" : "DestReg = imm;"})
     header_output += MicroLimmOpDeclare.subst(iop)
     decoder_output += MicroLimmOpConstructor.subst(iop)
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 52c13231c..c2aa27b67 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -231,17 +231,18 @@ let {{
             self.ext = 0
 
         def getAllocator(self, *microFlags):
-            allocator = '''new %(class_name)s(machInst, %(mnemonic)s,
-                    %(flags)s %(src1)s, %(src2)s, %(dest)s,
+            allocator = '''new %(class_name)s(machInst, "%(mnemonic)s"
+                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
                     %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
                 "class_name" : self.className,
                 "mnemonic" : self.mnemonic,
                 "flags" : self.microFlagsText(microFlags),
                 "src1" : self.src1, "src2" : self.src2,
                 "dest" : self.dest,
-                "setStatus" : self.setStatus,
+                "setStatus" : self.cppBool(self.setStatus),
                 "dataSize" : self.dataSize,
                 "ext" : self.ext}
+            return allocator
 
     class RegOpImm(X86Microop):
         def __init__(self, dest, src1, imm):
@@ -253,17 +254,18 @@ let {{
             self.ext = 0
 
         def getAllocator(self, *microFlags):
-            allocator = '''new %(class_name)s(machInst, %(mnemonic)s,
-                    %(flags)s %(src1)s, %(imm8)s, %(dest)s,
+            allocator = '''new %(class_name)s(machInst, "%(mnemonic)s"
+                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
                     %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
                 "class_name" : self.className,
                 "mnemonic" : self.mnemonic,
                 "flags" : self.microFlagsText(microFlags),
                 "src1" : self.src1, "imm8" : self.imm8,
                 "dest" : self.dest,
-                "setStatus" : self.setStatus,
+                "setStatus" : self.cppBool(self.setStatus),
                 "dataSize" : self.dataSize,
                 "ext" : self.ext}
+            return allocator
 }};
 
 let {{
@@ -290,7 +292,7 @@ let {{
         immCode = matcher.sub("imm8", code)
 
         # Build up the all register version of this micro op
-        iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode})
+        iop = InstObjParams(name, Name, 'X86MicroopBase', {"code" : regCode})
         header_output += MicroRegOpDeclare.subst(iop)
         decoder_output += MicroRegOpConstructor.subst(iop)
         exec_output += MicroRegOpExecute.subst(iop)
@@ -305,7 +307,7 @@ let {{
 
         # Build up the immediate version of this micro op
         iop = InstObjParams(name + "i", Name,
-                'X86MicroOpBase', {"code" : immCode})
+                'X86MicroopBase', {"code" : immCode})
         header_output += MicroRegOpImmDeclare.subst(iop)
         decoder_output += MicroRegOpImmConstructor.subst(iop)
         exec_output += MicroRegOpImmExecute.subst(iop)
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index a3ca7d91c..96fdf1c5e 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -69,7 +69,7 @@ def template MicroFaultExecute {{
 }};
 
 def template MicroFaultDeclare {{
-    class %(class_name)s : public X86MicroOpBase
+    class %(class_name)s : public X86MicroopBase
     {
       protected:
         Fault fault;
@@ -118,7 +118,7 @@ def template MicroFaultConstructor {{
 
 let {{
     # This microop takes in a single parameter, a fault to return.
-    iop = InstObjParams("fault", "GenFault", 'X86MicroOpBase', {"code" : ""})
+    iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""})
     header_output += MicroFaultDeclare.subst(iop)
     decoder_output += MicroFaultConstructor.subst(iop)
     exec_output += MicroFaultExecute.subst(iop)