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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:17:38 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:17:38 -0800 |
| commit | fcad6e3b13410ab6c7263ce42b5e657c16f79e1d (patch) | |
| tree | 7258842b1ecbc6752813df02a1d1a26eb5d29bb6 /src/arch/x86/isa/microops | |
| parent | e4ede69b2f97206d836719839221531f3e01149e (diff) | |
| download | gem5-fcad6e3b13410ab6c7263ce42b5e657c16f79e1d.tar.xz | |
X86: Add a wrattr microop.
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index f21621e30..4434f9e74 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1009,6 +1009,11 @@ let {{ SegSelDest = psrc1; ''' + class WrAttr(SegOp): + code = ''' + SegAttrDest = psrc1; + ''' + class Rdbase(SegOp): code = ''' DestReg = SegBaseSrc1; |