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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-20 16:39:07 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-20 16:39:07 -0700 |
| commit | 1ed6a8ed79d9a89437d47d52390aa5c7a8ebd5d5 (patch) | |
| tree | 5961c34d748a6b9e9a74e8c532f4a429f9b788ee /src/arch/x86/isa/microops | |
| parent | 705a22b999b92283ab1df0c7b3476022f8b0c0d2 (diff) | |
| download | gem5-1ed6a8ed79d9a89437d47d52390aa5c7a8ebd5d5.tar.xz | |
Define and fill out a lot of different instructions and instruction versions. Added two of the shift microops.
--HG--
extra : convert_revision : 0b76953dbb1dc3366242d4d209cccebde86bbe4e
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index a0e8adc9a..31ca8344d 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -389,10 +389,20 @@ let {{ defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True) defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True) - defineMicroRegOp('mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)') + defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)') defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', elseCode='DestReg=DestReg;', cc=True) + # Shift instructions + defineMicroRegOp('Sll', ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3))); + DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize); + ''') + # There are special rules for the flag for a single bit shift + defineMicroRegOp('Bll', ''' + DestReg = merge(DestReg, SrcReg1 << 1, dataSize); + ''') + # This has it's own function because Wr ops have implicit destinations def defineMicroRegOpWr(mnemonic, code, elseCode=";"): Name = mnemonic |