The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.

1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
    Implemented polymorphic microops and changed around the microcode assembler syntax.

--HG--
extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43

2 files changed, 176 insertions, 1 deletions

diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
new file mode 100644
index 000000000..b1351d999
--- /dev/null
+++ b/src/arch/x86/isa/microops/base.isa
@@ -0,0 +1,172 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use.  Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+//     Director of Intellectual Property Licensing
+//     Office of Strategy and Technology
+//     Hewlett-Packard Company
+//     1501 Page Mill Road
+//     Palo Alto, California  94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.  Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.  Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.  No right of
+// sublicense is granted herewith.  Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses.  Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//The operand types a microop template can be specialized with
+output header {{
+    enum OperandType {
+        RegisterOperand,
+        ImmediateOperand
+    };
+}};
+
+//A class which is the base of all x86 micro ops it provides a function to
+//set necessary flags appropriately.
+output header {{
+    class X86MicroOpBase : public X86StaticInst
+    {
+      protected:
+        X86MicroOpBase(bool isMicro, bool isDelayed,
+                bool isFirst, bool isLast,
+                const char *mnem, ExtMachInst _machInst,
+                OpClass __opClass) :
+            X86StaticInst(mnem, _machInst, __opClass)
+        {
+            flags[IsMicroOp] = isMicro;
+            flags[IsDelayedCommit] = isDelayed;
+            flags[IsFirstMicroOp] = isFirst;
+            flags[IsLastMicroOp] = isLast;
+        }
+    };
+}};
+
+// This sets up a class which is templated on the type of
+// arguments a particular flavor of a microcode instruction
+// can accept. It's parameters are specialized to create polymorphic
+// behavior in microops.
+def template BaseMicroOpTemplateDeclare {{
+    template%(signature)s
+    class %(class_name)s;
+}};
+
+let {{
+    def buildBaseMicroOpTemplate(Name, numParams):
+        signature = "<"
+        signature += "int SignatureOperandTypeSpecifier0"
+        for count in xrange(1,numParams):
+            signature += \
+                ", int SingatureOperandTypeSpecifier%d" % count
+        signature += ">"
+        subs = {"signature" : signature, "class_name" : Name}
+        return BaseMicroOpTemplateDeclare.subst(subs)
+
+    RegOpType = "RegisterOperand"
+    ImmOpType = "ImmediateOperand"
+
+    def buildMicroOpTemplateDict(*params):
+        signature = "<"
+        if len(params):
+            signature += params[0]
+            if len(params) > 1:
+                for param in params[1:]:
+                    signature += ", %s" % param
+        signature += ">"
+        subs = {"param_dec" : "", "param_arg_dec" : "",
+                "param_init" : "", "signature" : signature}
+        for count in xrange(len(params)):
+            subs["param_dec"] += "uint64_t param%d;\n" % count
+            subs["param_arg_dec"] += ", uint64_t _param%d" % count
+            subs["param_init"] += ", param%d(_param%d)" % (count, count)
+        return subs
+}};
+
+// A tmeplate for building a specialized version of the microcode
+// instruction which knows specifies which arguments it wants
+def template MicroOpDeclare {{
+    template<>
+    class %(class_name)s%(signature)s : public X86MicroOpBase
+    {
+      protected:
+        %(param_dec)s
+        void buildMe();
+
+      public:
+        %(class_name)s(bool isMicro, bool isDelayed,
+                bool isFirst, bool isLast,
+                ExtMachInst _machInst %(param_arg_dec)s);
+
+        %(class_name)s(ExtMachInst _machInst %(param_arg_dec)s);
+
+        %(BasicExecDeclare)s
+    };
+}};
+
+def template MicroOpConstructor {{
+
+    inline void %(class_name)s%(signature)s::buildMe()
+    {
+        %(constructor)s;
+    }
+
+    inline %(class_name)s%(signature)s::%(class_name)s(
+            ExtMachInst machInst %(param_arg_dec)s) :
+        %(base_class)s(false, false, false, false,
+                "%(mnemonic)s", machInst, %(op_class)s)
+                %(param_init)s
+    {
+        buildMe();
+    }
+
+    inline %(class_name)s%(signature)s::%(class_name)s(
+            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
+            ExtMachInst machInst %(param_arg_dec)s)
+        : %(base_class)s(isMicro, isDelayed, isFirst, isLast,
+                "%(mnemonic)s", machInst, %(op_class)s)
+                %(param_init)s
+    {
+        buildMe();
+    }
+}};
diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa
index bbf26f605..bb136fc81 100644
--- a/src/arch/x86/isa/microops/microops.isa
+++ b/src/arch/x86/isa/microops/microops.isa
@@ -53,5 +53,8 @@
 //
 // Authors: Gabe Black
 
-//Micro ops
+//Common microop stuff
+##include "base.isa"
+
+//Integer microop definitions
 ##include "int.isa"