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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:20:10 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:20:10 -0800 |
| commit | 8813168b5a3830b0b0a65b0342aca7b607e74b42 (patch) | |
| tree | c749075f955713dbbfb3c4333a6aad5065964731 /src/arch/x86/isa/microops | |
| parent | 28a35a6adbe083bbe7ff34dfe29d57a408f18bdb (diff) | |
| download | gem5-8813168b5a3830b0b0a65b0342aca7b607e74b42.tar.xz | |
X86: Do a merge for the zero extension microop.
Diffstat (limited to 'src/arch/x86/isa/microops')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index ceecfbf1c..fd2a3a64f 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -921,7 +921,7 @@ let {{ ''' class Zext(RegOp): - code = 'DestReg = bits(psrc1, op2, 0);' + code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' class Rddr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): |