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authorGabe Black <gblack@eecs.umich.edu>2007-09-04 23:33:50 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-04 23:33:50 -0700
commitd2fc4ee6258af274131e00d98ec44d199601596f (patch)
tree76aecb09162bc17fbec3419cd3df027a49f958a5 /src/arch/x86/isa/microops
parent8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7 (diff)
downloadgem5-d2fc4ee6258af274131e00d98ec44d199601596f.tar.xz
X86: Implement some SSE fp microops and instructions.
--HG-- extra : convert_revision : 7e0595ef542fbfb701bfac7e9ac4648349a92b26
Diffstat (limited to 'src/arch/x86/isa/microops')
-rw-r--r--src/arch/x86/isa/microops/regop.isa14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 3641438f5..1d9299ff3 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -655,4 +655,18 @@ let {{
int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
DestReg = merge(DestReg, intSrcReg1, dataSize);
'''
+
+ # These need to consider size at some point. They'll always use doubles
+ # for the moment.
+ class addfp(RegOp):
+ code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;'
+
+ class mulfp(RegOp):
+ code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;'
+
+ class divfp(RegOp):
+ code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;'
+
+ class subfp(RegOp):
+ code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;'
}};