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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-04 15:59:20 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-04 15:59:20 +0000 |
| commit | 41bc0fc5b27b97f6235e5cd3fe089ff43b588bef (patch) | |
| tree | 7c29765ea484fd0fde4a6d82b0f03aba3203c856 /src/arch/x86/isa/operands.isa | |
| parent | e47f1667b6f5f3b329c171a10d571696bd24b045 (diff) | |
| download | gem5-41bc0fc5b27b97f6235e5cd3fe089ff43b588bef.tar.xz | |
Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.
src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
--HG--
extra : convert_revision : cab66be59ed758b192226af17eddd5a86aa190f3
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index af469ab3d..1564c23e9 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,6 +96,9 @@ def operand_types {{ }}; def operands {{ + 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), + 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), + 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), |