Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.

--HG--
extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d

1 files changed, 5 insertions, 3 deletions

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 1564c23e9..b2ac17d66 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -99,7 +99,9 @@ def operands {{
         'DestReg':       ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
         'SrcReg1':       ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
         'SrcReg2':       ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
-        'IntRegOp0':     ('IntReg', 'udw', 'param0', 'IsInteger', 1),
-        'IntRegOp1':     ('IntReg', 'udw', 'param1', 'IsInteger', 2),
-        'IntRegOp2':     ('IntReg', 'udw', 'param2', 'IsInteger', 2),
+        'Base':          ('IntReg', 'uqw', 'base', 'IsInteger', 4),
+        'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
+        'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
+        'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
+        'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};