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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:27:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:27:55 -0700 |
| commit | a75b6f51060ceaa52014aa4dd6aadc6ca83365f8 (patch) | |
| tree | a8da313b6cf771f07ab0e1b795ea6be3137d4e29 /src/arch/x86/isa/operands.isa | |
| parent | f3f3747431e001dc6c80da5b6489516b610c22d6 (diff) | |
| download | gem5-a75b6f51060ceaa52014aa4dd6aadc6ca83365f8.tar.xz | |
X86: Move the fp microops to their own file with their own base classes in C++ and python.
--HG--
extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 05a9f4418..8c0eacca2 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,10 +96,13 @@ def operand_types {{ def operands {{ 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1), + 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1), 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2), + 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1), 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3), 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4), 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), + 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), |