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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-01-06 23:55:46 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-01-06 23:55:46 -0800 |
| commit | b23633ad1b3210d54386a9bab8c453f2bb4b7874 (patch) | |
| tree | 7c0b16dd98c346051dfc512aea2f664151d96eff /src/arch/x86/isa/operands.isa | |
| parent | 115b1a7ed350b9f1171b3f1b39c4c0875d1c0a5f (diff) | |
| download | gem5-b23633ad1b3210d54386a9bab8c453f2bb4b7874.tar.xz | |
X86: Hook in the M5 pseudo insts.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 343b37d41..a409d1f0f 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -113,6 +113,10 @@ def operands {{ 'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13), 'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14), 'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15), + 'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16), + 'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17), + 'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18), + 'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19), 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), |