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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:50:25 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:50:25 -0400 |
| commit | d4e7c7edd35d1f5e6771077eeca83369c1169a33 (patch) | |
| tree | 6f452b3223faffa2ee4210b2cbb6412db2fb7bdb /src/arch/x86/isa/operands.isa | |
| parent | fa7c81c6df5fdc1a17ffebbf431cb57ac84d79d0 (diff) | |
| download | gem5-d4e7c7edd35d1f5e6771077eeca83369c1169a33.tar.xz | |
X86: Keep handy values like the operating mode in one register.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index f002b2cea..446580c1b 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -151,5 +151,6 @@ def operands {{ 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207), 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208), 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209), + 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300) }}; |