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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-07 15:19:26 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-07 15:19:26 -0700 |
| commit | fb6cdf09cb4cfe9f39fdc7381168883fae6816ec (patch) | |
| tree | 749d30835f7f27edbd21f913e057c9bc922eb528 /src/arch/x86/isa/operands.isa | |
| parent | cae8d20633c0f43fdae23576adfb894284a7ee86 (diff) | |
| download | gem5-fb6cdf09cb4cfe9f39fdc7381168883fae6816ec.tar.xz | |
X86: Make a microcode branch microop.
Also some touch up for ruflag.
--HG--
extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 64179ca98..098a75370 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -104,7 +104,9 @@ def operands {{ 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6), 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), - 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), + 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11), + 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12), + 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |