The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.

1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
    Implemented polymorphic microops and changed around the microcode assembler syntax.

--HG--
extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43

1 files changed, 3 insertions, 3 deletions

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 36b0ee4df..af469ab3d 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
 }};
 
 def operands {{
-        'IntRegOp0':     ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
-        'IntRegOp1':     ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
-        'IntRegOp2':     ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
+        'IntRegOp0':     ('IntReg', 'udw', 'param0', 'IsInteger', 1),
+        'IntRegOp1':     ('IntReg', 'udw', 'param1', 'IsInteger', 2),
+        'IntRegOp2':     ('IntReg', 'udw', 'param2', 'IsInteger', 2),
 }};