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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-07 10:13:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-07 10:13:20 -0700 |
| commit | 3a55fc5cace5fdf744a891c6d32c4a9d4c10694a (patch) | |
| tree | 36695ff44c29ff0b249d66e4fc05957e903c45ed /src/arch/x86/isa/operands.isa | |
| parent | 62a2e85c9a0af39970568b35afa4d050ef571b23 (diff) | |
| download | gem5-3a55fc5cace5fdf744a891c6d32c4a9d4c10694a.tar.xz | |
X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 5ea803bfc..135fc10df 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -127,6 +127,7 @@ def operands {{ 'Quotient': impIntReg(2, 9), 'Remainder': impIntReg(3, 10), 'Divisor': impIntReg(4, 11), + 'DoubleBits': impIntReg(5, 11), 'Rax': intReg('(INTREG_RAX)', 12), 'Rbx': intReg('(INTREG_RBX)', 13), 'Rcx': intReg('(INTREG_RCX)', 14), |