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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-11 13:15:46 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-11 13:15:46 -0500 |
| commit | 5c940fec0aebcce5f81063f195220184918b377b (patch) | |
| tree | c9e754107957d63e7331ef13d2527a3874524393 /src/arch/x86/isa/operands.isa | |
| parent | 82f600e02ded4d7162dd9286f790462b9ab5d554 (diff) | |
| download | gem5-5c940fec0aebcce5f81063f195220184918b377b.tar.xz | |
x86: implement some of the x87 instructions
This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index b3607417b..79b59dbc3 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -163,6 +163,7 @@ def operands {{ 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'), + 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |