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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 00:27:23 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 00:27:23 -0800 |
| commit | d3e021820eb9916d63b96ba732ccc0783626433b (patch) | |
| tree | 56ba937d0260fd3366ed82c13af4d3698626bb0b /src/arch/x86/isa/operands.isa | |
| parent | 4c9b023a7afec8ba3a89736a01f445fc3e6adb05 (diff) | |
| download | gem5-d3e021820eb9916d63b96ba732ccc0783626433b.tar.xz | |
X86: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 25b73a8f2..51b9b73a6 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -97,7 +97,11 @@ def operands {{ 'FpSrcReg2': floatReg('src2', 21), 'FpDestReg': floatReg('dest', 22), 'FpData': floatReg('data', 23), - 'PCS': ('PCState', 'udw', None, + 'RIP': ('PCState', 'uqw', 'pc', + (None, None, 'IsControl'), 50), + 'NRIP': ('PCState', 'uqw', 'npc', + (None, None, 'IsControl'), 50), + 'nuIP': ('PCState', 'uqw', 'nupc', (None, None, 'IsControl'), 50), # This holds the condition code portion of the flag register. The # nccFlagBits version holds the rest. |