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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-15 00:14:20 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-15 00:14:20 -0500 |
| commit | 375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8 (patch) | |
| tree | 525cf56502718b69fb7f0e78162a8d5e63256489 /src/arch/x86/isa/operands.isa | |
| parent | 2820a448e2bcb861d099b1256087004462b78895 (diff) | |
| parent | 7c8e4ca3a3b66becbc3e4e7b5e106f5c44b09b6f (diff) | |
| download | gem5-375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8.tar.xz | |
branch merge
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 8c0eacca2..f50e71727 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -122,5 +122,10 @@ def operands {{ # instructions don't map their indexes with an old value. 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), + 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 71), + 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72), + 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73), + 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74), + 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |