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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:25:43 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:25:43 -0500 |
commit | 6369df59c85870c0975bc881d7b7d612c9dcf15b (patch) | |
tree | 0037bd2955043db5b60c5b967161ed45d30c5d21 /src/arch/x86/isa/operands.isa | |
parent | 3700e5448a947197f16e6da07368cbe5fe783fd6 (diff) | |
download | gem5-6369df59c85870c0975bc881d7b7d612c9dcf15b.tar.xz |
x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since it
is not being used any where in the implementation, it creates an unnecessary
dependency. Hence, it is being moved to a separate register.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
-rw-r--r-- | src/arch/x86/isa/operands.isa | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 8e2ae7fd4..e0cd2d628 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -120,12 +120,13 @@ def operands {{ # nccFlagBits version holds the rest. 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), - 'ecfBit': intReg('INTREG_PSEUDO(2)', 62), - 'ezfBit': intReg('INTREG_PSEUDO(3)', 63), + 'dfBit': intReg('INTREG_PSEUDO(2)', 62), + 'ecfBit': intReg('INTREG_PSEUDO(3)', 63), + 'ezfBit': intReg('INTREG_PSEUDO(4)', 64), # These register should needs to be more protected so that later # instructions don't map their indexes with an old value. - 'nccFlagBits': controlReg('MISCREG_RFLAGS', 64), - 'TOP': controlReg('MISCREG_X87_TOP', 65, ctype='ub'), + 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), + 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |