diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 22:55:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 22:55:55 -0700 |
| commit | a2e0d539d89643ce5243be9b8a0be4c3bcee7520 (patch) | |
| tree | 977feb73d3ed84cb3f0ad12efdf8e929e4a59397 /src/arch/x86/isa/operands.isa | |
| parent | 9e8e2f9ec6ae4ea3be8f5280a1ca4cb734e3e068 (diff) | |
| download | gem5-a2e0d539d89643ce5243be9b8a0be4c3bcee7520.tar.xz | |
X86: Add wrval/rdval microops for reading significant miscregs.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 8bb7c5bb1..343b37d41 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -153,7 +153,9 @@ def operands {{ 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206), 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207), 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208), - 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209), - 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210), + 'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209), + 'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210), + 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211), + 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300) }}; |