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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:20 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:20 -0600 |
| commit | 7f5463539b291b237647d3eceb7ca0276d487987 (patch) | |
| tree | 89726957ab8e2e3789750530b11474d133a8113a /src/arch/x86/isa/operands.isa | |
| parent | 91b00d98a5973d47b831495f5c668bbb185c7a15 (diff) | |
| download | gem5-7f5463539b291b237647d3eceb7ca0276d487987.tar.xz | |
x86: implements emms instruction
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index bc6d1886c..b3607417b 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -162,6 +162,7 @@ def operands {{ # Registers related to the state of x87 floating point unit. 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), + 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |