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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-13 16:34:46 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-13 16:34:46 -0700 |
| commit | f7b6230d99e102f3a6195687fed0617005a70424 (patch) | |
| tree | 360dd76c0b7d7f159e816af90ab8fb3e62f3c36c /src/arch/x86/isa/operands.isa | |
| parent | 0f57b407a3df68f93e73e0635569d7bf5dd151b0 (diff) | |
| download | gem5-f7b6230d99e102f3a6195687fed0617005a70424.tar.xz | |
X86: Total overhaul of the division instructions and microops.
--HG--
extra : convert_revision : 303ea45f69f7805361ad877fe6bb43fbc3dfd7a6
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index fae1aa5ca..7b0427b44 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -105,7 +105,8 @@ def operands {{ 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9), 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10), - 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 11), + 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11), + 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12), 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), |