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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:19 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:19 -0600 |
| commit | 91b00d98a5973d47b831495f5c668bbb185c7a15 (patch) | |
| tree | d2108f83a8be89fdaeec5120c5f5ccb6744cdba1 /src/arch/x86/isa/operands.isa | |
| parent | 7fdcfdf08b9d654fcf311b213bd729cb957f822c (diff) | |
| download | gem5-91b00d98a5973d47b831495f5c668bbb185c7a15.tar.xz | |
x86: implement fabs, fchs instructions
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 05b127e37..bc6d1886c 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -158,7 +158,11 @@ def operands {{ # These register should needs to be more protected so that later # instructions don't map their indexes with an old value. 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), + + # Registers related to the state of x87 floating point unit. 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), + 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), + # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |