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authorGabe Black <gblack@eecs.umich.edu>2007-04-06 14:37:46 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-06 14:37:46 +0000
commit3c9768e6448b72689e9edb250dd0ee3e5eadb9d7 (patch)
treef950d270e92348f95e3464cf51de4003510c9f07 /src/arch/x86/isa/operands.isa
parenta664017c2a839279f8b8eea1076bba47d1863b88 (diff)
parent077183f7ece6aa7fcb009fb078e2e1a3370f9327 (diff)
downloadgem5-3c9768e6448b72689e9edb250dd0ee3e5eadb9d7.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : b7e89d32df946ea24c438292308f5fc8248f8bd9
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
-rw-r--r--src/arch/x86/isa/operands.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 36b0ee4df..af469ab3d 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
}};
def operands {{
- 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
- 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
- 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
+ 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1),
+ 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2),
+ 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2),
}};