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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:29:53 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:29:53 -0500 |
commit | 4d4d212ae974b3a3ad6d185902d4896c0233a8d9 (patch) | |
tree | 4a8203c6677714b5996b6dc22178c61bdb07dec9 /src/arch/x86/isa/operands.isa | |
parent | 16a559c9c66b3e810860b59c4099527b38a5337e (diff) | |
download | gem5-4d4d212ae974b3a3ad6d185902d4896c0233a8d9.tar.xz |
X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
-rw-r--r-- | src/arch/x86/isa/operands.isa | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index e0ace11d0..8e2ae7fd4 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -119,10 +119,13 @@ def operands {{ # This holds the condition code portion of the flag register. The # nccFlagBits version holds the rest. 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), + 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), + 'ecfBit': intReg('INTREG_PSEUDO(2)', 62), + 'ezfBit': intReg('INTREG_PSEUDO(3)', 63), # These register should needs to be more protected so that later # instructions don't map their indexes with an old value. - 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), - 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), + 'nccFlagBits': controlReg('MISCREG_RFLAGS', 64), + 'TOP': controlReg('MISCREG_X87_TOP', 65, ctype='ub'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |