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authorGabe Black <gblack@eecs.umich.edu>2007-06-20 15:02:50 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-06-20 15:02:50 +0000
commita68ddf685c739220d09fdc44000dd217d0707f8e (patch)
tree5026458b55d8032a56b52bba3dc35a4281e540c7 /src/arch/x86/isa/specialize.isa
parentd2ccf5e50917701a4eab9f1848c8d524ccf0c7cc (diff)
downloadgem5-a68ddf685c739220d09fdc44000dd217d0707f8e.tar.xz
Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.
--HG-- extra : convert_revision : 1212b8463eab1c1dcba7182c487d1e9184cf9bea
Diffstat (limited to 'src/arch/x86/isa/specialize.isa')
-rw-r--r--src/arch/x86/isa/specialize.isa39
1 files changed, 15 insertions, 24 deletions
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index bb2be47d9..10e57ba18 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -85,7 +85,7 @@ let {{
let {{
class OpType(object):
- parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))")
+ parser = re.compile(r"(?P<tag>[A-Z]+)(?P<size>[a-z]*)|(r(?P<reg>[A-Z0-9]+)(?P<rsize>[a-z]*))")
def __init__(self, opTypeString):
match = OpType.parser.search(opTypeString)
if match == None:
@@ -105,14 +105,15 @@ let {{
while len(opTypes):
# Parse the operand type string we're working with
opType = OpType(opTypes[0])
+ opTypes.pop(0)
if opType.reg:
#Figure out what to do with fixed register operands
#This is the index to use, so we should stick it some place.
if opType.reg in ("A", "B", "C", "D"):
- env.addReg("INTREG_R%sX" % opType.reg)
+ env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg)
else:
- env.addReg("INTREG_R%s" % opType.reg)
+ env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg)
if opType.size:
if opType.rsize in ("l", "h", "b"):
print "byte"
@@ -121,6 +122,11 @@ let {{
else:
print "Didn't recognize fixed register size %s!" % opType.rsize
Name += "_R"
+ elif opType.tag == "M":
+ # This refers to memory. The macroop constructor sets up modrm
+ # addressing. Non memory modrm settings should cause an error.
+ Name += "_M"
+ env.doModRM = True
elif opType.tag == None or opType.size == None:
raise Exception, "Problem parsing operand tag: %s" % opType.tag
elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
@@ -130,39 +136,24 @@ let {{
elif opType.tag in ("E", "Q", "W"):
# This might refer to memory or to a register. We need to
# divide it up farther.
- regTypes = copy.copy(opTypes)
- regTypes.pop(0)
regEnv = copy.copy(env)
regEnv.addReg(ModRMRMIndex)
- regName = Name + "_R"
- # This needs to refer to memory, but we'll fill in the details
- # later. It needs to take into account unaligned memory
- # addresses.
- memTypes = copy.copy(opTypes)
- memTypes.pop(0)
+ # This refers to memory. The macroop constructor should set up
+ # modrm addressing.
memEnv = copy.copy(env)
- memName = Name + "_M"
- print "%0"
+ memEnv.doModRM = True
return doSplitDecode(specializeInst, "MODRM_MOD",
- {"3" : (regName, regTypes, regEnv)},
- (memName, memTypes, memEnv))
+ {"3" : (Name + "_R", copy.copy(opTypes), regEnv)},
+ (Name + "_M", copy.copy(opTypes), memEnv))
elif opType.tag in ("I", "J"):
# Immediates
Name += "_I"
- elif opType.tag == "M":
- # This needs to refer to memory, but we'll fill in the details
- # later. It needs to take into account unaligned memory
- # addresses.
- print "%0"
- Name += "_M"
elif opType.tag in ("PR", "R", "VR"):
- # There should probably be a check here to verify that mod
- # is equal to 11b
+ # Non register modrm settings should cause an error
env.addReg(ModRMRMIndex)
Name += "_R"
else:
raise Exception, "Unrecognized tag %s." % opType.tag
- opTypes.pop(0)
# Generate code to return a macroop of the given name which will
# operate in the "emulation environment" env