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authorGabe Black <gblack@eecs.umich.edu>2007-12-01 23:03:39 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-01 23:03:39 -0800
commitdc6f96017135da7f3beae5055195de3cf8e47c6c (patch)
treeb8fad747c652fe34db462bf585be4d184da02d6b /src/arch/x86/isa/specialize.isa
parenta548067b01ed99d4abc9483ca11466d3d9d4ceca (diff)
downloadgem5-dc6f96017135da7f3beae5055195de3cf8e47c6c.tar.xz
X86: Reorganize segmentation and implement segment selector movs.
--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
Diffstat (limited to 'src/arch/x86/isa/specialize.isa')
-rw-r--r--src/arch/x86/isa/specialize.isa8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 3802d8949..abf734307 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -154,12 +154,18 @@ let {{
elif opType.tag == None or opType.size == None:
raise Exception, "Problem parsing operand tag: %s" % opType.tag
elif opType.tag == "C":
+ # A control register indexed by the "reg" field
env.addReg(ModRMRegIndex)
Name += "_C"
elif opType.tag == "D":
+ # A debug register indexed by the "reg" field
env.addReg(ModRMRegIndex)
Name += "_D"
- elif opType.tag in ("G", "P", "S", "T", "V"):
+ elif opType.tag == "S":
+ # A segment selector register indexed by the "reg" field
+ env.addReg(ModRMRegIndex)
+ Name += "_S"
+ elif opType.tag in ("G", "P", "T", "V"):
# Use the "reg" field of the ModRM byte to select the register
env.addReg(ModRMRegIndex)
Name += "_R"