Implement a handful more instructions and differentiate macroops based on the operand types they expect.

--HG--
extra : convert_revision : f9c8e694a8c0eb33b988657dca03ab495b65bee8

1 files changed, 13 insertions, 5 deletions

diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 96add3ab5..faf863351 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -66,16 +66,16 @@ let {{
     # vals is a dict which matches case values with what should be decoded to.
     # builder is called on the exploded contents of "vals" values to generate
     # whatever code should be used.
-    def doSplitDecode(Name, builder, switchVal, vals, default = None):
+    def doSplitDecode(builder, switchVal, vals, default = None):
         blocks = OutputBlocks()
         blocks.decode_block = 'switch(%s) {\n' % switchVal
         for (val, todo) in vals.items():
-            new_blocks = builder(Name, *todo)
+            new_blocks = builder(*todo)
             new_blocks.decode_block = \
                 '\tcase %s: %s\n' % (val, new_blocks.decode_block)
             blocks.append(new_blocks)
         if default:
-            new_blocks = builder(Name, *default)
+            new_blocks = builder(*default)
             new_blocks.decode_block = \
                 '\tdefault: %s\n' % new_blocks.decode_block
             blocks.append(new_blocks)
@@ -120,11 +120,13 @@ let {{
                         print "word"
                     else:
                         print "Didn't recognize fixed register size %s!" % opType.rsize
+                Name += "_R"
             elif opType.tag == None or opType.size == None:
                 raise Exception, "Problem parsing operand tag: %s" % opType.tag
             elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
                 # Use the "reg" field of the ModRM byte to select the register
                 env.addReg(ModRMRegIndex)
+                Name += "_R"
             elif opType.tag in ("E", "Q", "W"):
                 # This might refer to memory or to a register. We need to
                 # divide it up farther.
@@ -132,27 +134,33 @@ let {{
                 regTypes.pop(0)
                 regEnv = copy.copy(env)
                 regEnv.addReg(ModRMRMIndex)
+                regName = Name + "_R"
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
                 memTypes = copy.copy(opTypes)
                 memTypes.pop(0)
                 memEnv = copy.copy(env)
+                memName = Name + "_M"
                 print "%0"
-                return doSplitDecode(Name, specializeInst, "MODRM_MOD",
-                    {"3" : (regTypes, regEnv)}, (memTypes, memEnv))
+                return doSplitDecode(specializeInst, "MODRM_MOD",
+                    {"3" : (regName, regTypes, regEnv)},
+                    (memName, memTypes, memEnv))
             elif opType.tag in ("I", "J"):
                 # Immediates
                 print "IMMEDIATE"
+                Name += "_I"
             elif opType.tag == "M":
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
                 print "%0"
+                Name += "_M"
             elif opType.tag in ("PR", "R", "VR"):
                 # There should probably be a check here to verify that mod
                 # is equal to 11b
                 env.addReg(ModRMRMIndex)
+                Name += "_R"
             else:
                 raise Exception, "Unrecognized tag %s." % opType.tag
             opTypes.pop(0)