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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
| commit | f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72 (patch) | |
| tree | 7215bb386591b8ff8d3ce53cefd40599c1a44c2a /src/arch/x86/isa/specialize.isa | |
| parent | 4d4d2883f9c84f0cebec4b65479c11540dbb36f7 (diff) | |
| download | gem5-f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72.tar.xz | |
X86: Implement the wrcr microop which writes a control register, and some control register work.
--HG--
extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab
Diffstat (limited to 'src/arch/x86/isa/specialize.isa')
| -rw-r--r-- | src/arch/x86/isa/specialize.isa | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index cf6b6ff86..3802d8949 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -153,7 +153,13 @@ let {{ return doRipRelativeDecode(Name, opTypes, env) elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag - elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): + elif opType.tag == "C": + env.addReg(ModRMRegIndex) + Name += "_C" + elif opType.tag == "D": + env.addReg(ModRMRegIndex) + Name += "_D" + elif opType.tag in ("G", "P", "S", "T", "V"): # Use the "reg" field of the ModRM byte to select the register env.addReg(ModRMRegIndex) Name += "_R" |