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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:49 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:49 -0500 |
| commit | 4ccdf8fb81ff670f111428c31b9741c926d87d20 (patch) | |
| tree | 52e7191365e3da35302d2afeedebf38d310ffc4e /src/arch/x86/isa | |
| parent | b4dade6fb273baaf86d316ca90fba5ebc7d4b717 (diff) | |
| download | gem5-4ccdf8fb81ff670f111428c31b9741c926d87d20.tar.xz | |
x86: set op class of two fp instructions
This patch sets op class of two fp instructions: movfp and pop x87 stack
as IntAluOp since these instructions do not make use of the fp alu.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 4155fe3aa..39162d392 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -270,6 +270,7 @@ let {{ else_code = 'FpDestReg_uqw = FpDestReg_uqw;' cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \ ecfBit | ezfBit, src2)" + op_class = 'IntAluOp' class Xorfp(FpBinaryOp): code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;' @@ -449,4 +450,5 @@ let {{ spm=spm, SetStatus=False, UpdateFTW=UpdateFTW) code = '' + op_class = 'IntAluOp' }}; |