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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:50:05 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:50:05 -0400
commit6bd9cf3594b0150c8cb39a23ca2cfb465b6e09bb (patch)
treeaa9eac2d51747217854b39b62c6bd8297d844e1b /src/arch/x86/isa
parente0c20386ac0f8f54db2e8947793b4c2debabcefc (diff)
downloadgem5-6bd9cf3594b0150c8cb39a23ca2cfb465b6e09bb.tar.xz
X86: Add a microop to read a segments attribute register.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/regop.isa5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 0187567e9..48aecf138 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1008,6 +1008,11 @@ let {{
DestReg = SegLimitSrc1;
'''
+ class RdAttr(SegOp):
+ code = '''
+ DestReg = SegAttrSrc1;
+ '''
+
class Rdsel(SegOp):
code = '''
DestReg = SegSelSrc1;