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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:39:10 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:39:10 -0400
commit8501a90f59c73896b4eea6d7ce8f1d1cc8685d53 (patch)
tree6e8be3ff12c7092a551ca0e816f622083de39f8c /src/arch/x86/isa
parentd093fcb07924cc4341b8142c448b905dd94f7125 (diff)
downloadgem5-8501a90f59c73896b4eea6d7ce8f1d1cc8685d53.tar.xz
X86: Add in some support for the tsc register.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/system/msrs.py8
-rw-r--r--src/arch/x86/isa/microops/regop.isa12
-rw-r--r--src/arch/x86/isa/operands.isa3
4 files changed, 22 insertions, 3 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 8135a1fdb..e2d968c17 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -317,7 +317,7 @@
}
0x06: decode OPCODE_OP_BOTTOM3 {
0x0: Inst::WRMSR();
- 0x1: rdtsc();
+ 0x1: Inst::RDTSC();
0x2: Inst::RDMSR();
0x3: rdpmc();
0x4: sysenter();
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index 1acb4c792..461ed1054 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -99,4 +99,12 @@ def macroop WRMSR
or t2, t2, t3, dataSize=8
st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
};
+
+def macroop RDTSC
+{
+ rdtsc t1
+ mov rax, rax, t1, dataSize=4
+ srli t1, t1, 32, dataSize=8
+ mov rdx, rdx, t1, dataSize=4
+};
'''
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index e761f0034..03a7515ed 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2007 The Hewlett-Packard Development Company
+// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// Redistribution and use of this software in source and binary forms,
@@ -1018,6 +1018,16 @@ let {{
'''
+ class Wrtsc(WrRegOp):
+ code = '''
+ TscOp = psrc1;
+ '''
+
+ class Rdtsc(RdRegOp):
+ code = '''
+ DestReg = TscOp;
+ '''
+
class Wrdl(RegOp):
code = '''
SegDescriptor desc = SrcReg1;
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 9345158e9..87fd28a6a 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -26,7 +26,7 @@
//
// Authors: Gabe Black
-// Copyright (c) 2007 The Hewlett-Packard Development Company
+// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// Redistribution and use of this software in source and binary forms,
@@ -146,5 +146,6 @@ def operands {{
'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
+ 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 208),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
}};