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authorGabe Black <gblack@eecs.umich.edu>2007-07-24 15:10:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-24 15:10:20 -0700
commit15f57bd7cb84892809f6a9793d11ea27895e9b31 (patch)
tree1c5709ca818dea6b1c37fd8df1360e1322cba73e /src/arch/x86/isa
parent66911a1fab9900768db67610346585245a484ef4 (diff)
downloadgem5-15f57bd7cb84892809f6a9793d11ea27895e9b31.tar.xz
Fix immediate shifts. Implement register shifts.
--HG-- extra : convert_revision : 0b83422ad3c190021e46cada07e64d8d57d29859
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/insts/rotate_and_shift/shift.py78
1 files changed, 69 insertions, 9 deletions
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index 5a04317d9..b9c07b0ba 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -56,13 +56,13 @@
microcode = '''
def macroop SAL_R_I
{
- sll reg, reg, imm
+ slli reg, reg, imm
};
def macroop SAL_M_I
{
ld t1, ds, [scale, index, base], disp
- sll t1, t1, imm
+ slli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@@ -70,19 +70,39 @@ def macroop SAL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- sll t1, t1, imm
+ slli t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_R_R
+{
+ slli reg, reg, regm
+};
+
+def macroop SAL_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ slli t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ slli t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_R_I
{
- srl reg, reg, imm
+ srli reg, reg, imm
};
def macroop SHR_M_I
{
ld t1, ds, [scale, index, base], disp
- srl t1, t1, imm
+ srli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@@ -90,19 +110,39 @@ def macroop SHR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- srl t1, t1, imm
+ srli t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_R_R
+{
+ srli reg, reg, regm
+};
+
+def macroop SHR_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ srli t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ srli t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_R_I
{
- sra reg, reg, imm
+ srai reg, reg, imm
};
def macroop SAR_M_I
{
ld t1, ds, [scale, index, base], disp
- sra t1, t1, imm
+ srai t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@@ -110,7 +150,27 @@ def macroop SAR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- sra t1, t1, imm
+ srai t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_R_R
+{
+ srai reg, reg, regm
+};
+
+def macroop SAR_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ srai t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ srai t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
'''