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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:19 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:19 -0800 |
| commit | dfa8cbeb06b7556753c26b97978924c1f4a24699 (patch) | |
| tree | 5c47168bd2d8794612d385cc12277c5212660e40 /src/arch/x86/isa | |
| parent | c41fc138e78420c72d8dada805a16c96f74f631b (diff) | |
| download | gem5-dfa8cbeb06b7556753c26b97978924c1f4a24699.tar.xz | |
m5: added work completed monitoring support
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 1dc32122e..11cd6eeb1 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -216,6 +216,12 @@ 0x59: m5reserved5({{ warn("M5 reserved opcode 5 ignored.\n"); }}, IsNonSpeculative); + 0x5a: m5_work_begin({{ + PseudoInst::workbegin(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); + 0x5b: m5_work_end({{ + PseudoInst::workend(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); default: Inst::UD2(); } } |