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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-30 13:25:00 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-30 13:25:00 -0700 |
| commit | da84aa95a99ef84ff10b7ce53156825e73d0b8e5 (patch) | |
| tree | d815eb4f8ee8797f1de8e673987f466b1cb1731f /src/arch/x86/isa | |
| parent | d8beeff324f0d47927716e0081fe4a72c56601f7 (diff) | |
| download | gem5-da84aa95a99ef84ff10b7ce53156825e73d0b8e5.tar.xz | |
Make the register indices use the appropriate "fold" bit.
--HG--
extra : convert_revision : 89e15e2ef1f709f2c09238b78f94505ce8ef146d
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 406c74a1f..127e1b98a 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,13 +96,13 @@ def operand_types {{ }}; def operands {{ - 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), - 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), - 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), - 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4), - 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), - 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), - 'rax': ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7), + 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1), + 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2), + 'Base': ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3), + 'Index': ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4), + 'DestReg': ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5), + 'Data': ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6), + 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) |