X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.

There are no priviledge checks, so these instructions will all work in all
modes.

--HG--
extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393

5 files changed, 93 insertions, 14 deletions

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index eae994706..0482fdf23 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -211,9 +211,9 @@
                 default: Inst::UD2();
             }
             0x06: decode OPCODE_OP_BOTTOM3 {
-                0x0: wrmsr();
+                0x0: Inst::WRMSR();
                 0x1: rdtsc();
-                0x2: rdmsr();
+                0x2: Inst::RDMSR();
                 0x3: rdpmc();
                 0x4: sysenter();
                 0x5: sysexit();
diff --git a/src/arch/x86/isa/insts/system/__init__.py b/src/arch/x86/isa/insts/system/__init__.py
index 72e3bdf0a..6d4b3f3d1 100644
--- a/src/arch/x86/isa/insts/system/__init__.py
+++ b/src/arch/x86/isa/insts/system/__init__.py
@@ -53,7 +53,8 @@
 #
 # Authors: Gabe Black
 
-categories = ["undefined_operation"]
+categories = ["undefined_operation",
+              "msrs"]
 
 microcode = ""
 for category in categories:
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
new file mode 100644
index 000000000..ea576510b
--- /dev/null
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -0,0 +1,74 @@
+# Copyright (c) 2007 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use of this software in source and binary forms,
+# with or without modification, are permitted provided that the
+# following conditions are met:
+#
+# The software must be used only for Non-Commercial Use which means any
+# use which is NOT directed to receiving any direct monetary
+# compensation for, or commercial advantage from such use.  Illustrative
+# examples of non-commercial use are academic research, personal study,
+# teaching, education and corporate research & development.
+# Illustrative examples of commercial use are distributing products for
+# commercial advantage and providing services using the software for
+# commercial advantage.
+#
+# If you wish to use this software or functionality therein that may be
+# covered by patents for commercial use, please contact:
+#     Director of Intellectual Property Licensing
+#     Office of Strategy and Technology
+#     Hewlett-Packard Company
+#     1501 Page Mill Road
+#     Palo Alto, California  94304
+#
+# Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.  Redistributions
+# in binary form must reproduce the above copyright notice, this list of
+# conditions and the following disclaimer in the documentation and/or
+# other materials provided with the distribution.  Neither the name of
+# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.  No right of
+# sublicense is granted herewith.  Derivatives of the software and
+# output created using the software may be prepared, but only for
+# Non-Commercial Uses.  Derivatives of the software may be shared with
+# others provided: (i) the others agree to abide by the list of
+# conditions herein which includes the Non-Commercial Use restrictions;
+# and (ii) such Derivatives of the software include the above copyright
+# notice to acknowledge the contribution from this software where
+# applicable, this list of conditions and the disclaimer below.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+microcode = '''
+def macroop WRMSR
+{
+    limm t1, "IntAddrPrefixMSR >> 3"
+    ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+    mov rax, rax, t2, dataSize=4
+    srli t2, t2, 32, dataSize=8
+    mov rdx, rdx, t2, dataSize=4
+};
+
+def macroop RDMSR
+{
+    limm t1, "IntAddrPrefixMSR >> 3"
+    mov t2, t2, rdx, dataSize=4
+    slli t2, t2, 32, dataSize=8
+    mov t2, t2, rax, dataSize=4
+    st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+};
+'''
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index c8bc36b69..50135e30c 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -106,6 +106,10 @@ let {{
     assembler.symbols["riprel"] = \
         ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
 
+    # This segment selects an internal address space mapped to MSRs,
+    # CPUID info, etc.
+    assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
+
     for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
         assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
 
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 106a8a0fe..32fefb5fa 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{
 
 let {{
     class LdStOp(X86Microop):
-        def __init__(self, data, segment, addr, disp, dataSize):
+        def __init__(self, data, segment, addr, disp, dataSize, addressSize):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
             self.segment = segment
             self.dataSize = dataSize
-            self.addressSize = "env.addressSize"
+            self.addressSize = addressSize
 
         def getAllocator(self, *microFlags):
             allocator = '''new %(class_name)s(machInst, mnemonic
@@ -378,10 +378,10 @@ let {{
         exec_output += MicroLoadCompleteAcc.subst(iop)
 
         class LoadOp(LdStOp):
-            def __init__(self, data, segment, addr,
-                    disp = 0, dataSize="env.dataSize"):
+            def __init__(self, data, segment, addr, disp = 0,
+                    dataSize="env.dataSize", addressSize="env.addressSize"):
                 super(LoadOp, self).__init__(data, segment,
-                        addr, disp, dataSize)
+                        addr, disp, dataSize, addressSize)
                 self.className = Name
                 self.mnemonic = name
 
@@ -411,10 +411,10 @@ let {{
         exec_output += MicroStoreCompleteAcc.subst(iop)
 
         class StoreOp(LdStOp):
-            def __init__(self, data, segment, addr,
-                    disp = 0, dataSize="env.dataSize"):
+            def __init__(self, data, segment, addr, disp = 0,
+                    dataSize="env.dataSize", addressSize="env.addressSize"):
                 super(StoreOp, self).__init__(data, segment,
-                        addr, disp, dataSize)
+                        addr, disp, dataSize, addressSize)
                 self.className = Name
                 self.mnemonic = name
 
@@ -432,10 +432,10 @@ let {{
     exec_output += MicroLeaExecute.subst(iop)
 
     class LeaOp(LdStOp):
-        def __init__(self, data, segment, addr,
-                disp = 0, dataSize="env.dataSize"):
+        def __init__(self, data, segment, addr, disp = 0,
+                dataSize="env.dataSize", addressSize="env.addressSize"):
             super(LeaOp, self).__init__(data, segment,
-                    addr, disp, dataSize)
+                    addr, disp, dataSize, addressSize)
             self.className = "Lea"
             self.mnemonic = "lea"