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authorGabe Black <gblack@eecs.umich.edu>2007-06-21 15:28:08 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-06-21 15:28:08 +0000
commitae60d580835adbb1f91d8fbc48e186ffbcc4f323 (patch)
tree144e6d0b7bc21c749933fc08d77f6f2a4341e832 /src/arch/x86/isa
parent0dc15742e39a0054ca8eec93de27489e1f48ebfd (diff)
downloadgem5-ae60d580835adbb1f91d8fbc48e186ffbcc4f323.tar.xz
Define symbols for the x86 specialization of the microassembler.
--HG-- extra : convert_revision : 1fd66ba519d211fec18641b6df94b7640c56080c
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microasm.isa28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 50addb33f..4e06f4391 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -72,5 +72,33 @@ let {{
from micro_asm import MicroAssembler, Rom_Macroop, Rom
mainRom = Rom('main ROM')
assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
+ # Add in symbols for the microcode registers
+ for num in range(15):
+ assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
+ # Add in symbols for the segment descriptor registers
+ for letter in ("C", "D", "E", "F", "G", "S"):
+ assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
+ # Miscellaneous symbols
+ symbols = {
+ "reg" : "env.reg",
+ "regm" : "env.regm",
+ "imm" : "IMMEDIATE",
+ "disp" : "DISPLACEMENT",
+ "scale" : "env.scale",
+ "index" : "env.index",
+ "base" : "env.base",
+ "dsz" : "env.dataSize",
+ "osz" : "env.operandSize",
+ "ssz" : "env.stackSize"
+ }
+ assembler.symbols.update(symbols)
+
+ # Code literal which forces a default 64 bit operand size in 64 bit mode.
+ assembler.symbols["oszIn64Override"] = '''
+ if (machInst.mode.submode == SixtyFourBitMode &&
+ env.dataSize == 4)
+ env.dataSize = 8;
+ '''
+
macroopDict = assembler.assemble(microcode)
}};