diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:00:03 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:00:03 -0700 |
| commit | 64d794869271485b79123951d5b198b8a9b12885 (patch) | |
| tree | 2463988e7665930c35cfdb0ea9c30ee2a3d8b2e0 /src/arch/x86/isa | |
| parent | 88041f75c44680f07e707339afd8fb81526fd256 (diff) | |
| download | gem5-64d794869271485b79123951d5b198b8a9b12885.tar.xz | |
X86: Handle rotating right all the way around or more.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 85fe8fe51..2514be91a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -727,10 +727,11 @@ let {{ code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); - if(shiftAmt) + uint8_t realShiftAmt = shiftAmt % (dataSize * 8); + if(realShiftAmt) { - uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); - uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); + uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); + uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); } else |