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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:19:14 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:19:14 -0800 |
| commit | 5f0428ef9fc7acc5b1315f6c87202c1ee13f0b8b (patch) | |
| tree | 4a4014afe1f5b60ef3a836a9a77dd546d2e27056 /src/arch/x86/isa | |
| parent | eafdf00eb3c9b68cbf6c6fbedcd56010d747f975 (diff) | |
| download | gem5-5f0428ef9fc7acc5b1315f6c87202c1ee13f0b8b.tar.xz | |
X86: Use the right portion of a register for stores.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 097b0e311..a1aaddfe2 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -466,9 +466,9 @@ let {{ microopClasses[name] = StoreOp - defineMicroStoreOp('St', 'Mem = Data;') + defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') - defineMicroStoreOp('Stupd', 'Mem = Data;', + defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);', 'Base = merge(Base, EA - SegBase, addressSize);', 'Base = merge(Base, pkt->req->getVaddr() - SegBase, addressSize);'); defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") |