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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:59:25 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:59:25 -0700 |
| commit | 029d360db215ae081a2cba0b5552eaf77f509b20 (patch) | |
| tree | 7fdcdc6c26cc5effab9da5761faa7265efb732e5 /src/arch/x86/isa | |
| parent | 7f9a3af25014dd8f022968047a9f6f5198079a16 (diff) | |
| download | gem5-029d360db215ae081a2cba0b5552eaf77f509b20.tar.xz | |
X86: Make shifts/rotations that write to 32 bits of a register zero extend.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 447939abd..85fe8fe51 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -734,7 +734,7 @@ let {{ DestReg = merge(DestReg, top | bottom, dataSize); } else - DestReg = DestReg; + DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. @@ -771,7 +771,7 @@ let {{ DestReg = merge(DestReg, top | bottom, dataSize); } else - DestReg = DestReg; + DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. @@ -805,7 +805,7 @@ let {{ DestReg = merge(DestReg, top | bottom, dataSize); } else - DestReg = DestReg; + DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. @@ -844,7 +844,7 @@ let {{ DestReg = merge(DestReg, top | bottom, dataSize); } else - DestReg = DestReg; + DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. |