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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:15:16 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:15:16 -0700 |
| commit | 470dcef22920765a45b2bea77e26df57e8d3eef6 (patch) | |
| tree | e402089ad7c7f35cd8598134e217f550f25d0974 /src/arch/x86/isa | |
| parent | 31d29ee3f8209a43e325cfe0373e9081a263ad36 (diff) | |
| download | gem5-470dcef22920765a45b2bea77e26df57e8d3eef6.tar.xz | |
X86: Implement a "sum of absolute differences" microop.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 12dfa026c..bfa1577c2 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -948,6 +948,25 @@ let {{ FpDestReg.uqw = result; ''' + class Msad(MediaOp): + code = ''' + int srcBits = srcSize * 8; + int items = sizeof(FloatRegBits) / srcSize; + + uint64_t sum = 0; + for (int i = 0; i < items; i++) { + int hiIndex = (i + 1) * srcBits - 1; + int loIndex = (i + 0) * srcBits; + uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); + uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); + int64_t resBits = arg1Bits - arg2Bits; + if (resBits < 0) + resBits = -resBits; + sum += resBits; + } + FpDestReg.uqw = sum & mask(destSize * 8); + ''' + class Cvti2f(MediaOp): def __init__(self, dest, src, \ size = None, destSize = None, srcSize = None, ext = None): |