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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:39:14 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:39:14 -0800
commit917ae9ec668fde45c8cb614d9fac29df33892fa1 (patch)
treecd899f2a4272d2f0219fac8f74c79a26da7dce64 /src/arch/x86/isa
parent49507982685b4e807e612ff176fb67901415a2ce (diff)
downloadgem5-917ae9ec668fde45c8cb614d9fac29df33892fa1.tar.xz
X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.
--HG-- extra : convert_revision : f1eb17291f4c01f3c0fa8f99650bc1edf09d21de
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/insts/system/msrs.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index ea576510b..20b9b2a0b 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -54,7 +54,7 @@
# Authors: Gabe Black
microcode = '''
-def macroop WRMSR
+def macroop RDMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
@@ -63,7 +63,7 @@ def macroop WRMSR
mov rdx, rdx, t2, dataSize=4
};
-def macroop RDMSR
+def macroop WRMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
mov t2, t2, rdx, dataSize=4