diff options
| author | Gabe Black <gabeblack@google.com> | 2018-03-12 17:46:52 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-03-14 20:08:54 +0000 |
| commit | 497ebfe98578b71d22f979b848c4b873f05ec6ee (patch) | |
| tree | eef0c1aab82910f55e8c44f95cd96c1cbf070f4c /src/arch/x86/isa | |
| parent | ea383880c61023360aee672c6197f2cda9889f07 (diff) | |
| download | gem5-497ebfe98578b71d22f979b848c4b873f05ec6ee.tar.xz | |
x86: Simplify the implementations of RDTSC and RDTSCP slightly.
These instructions originally read the TSC into t1 and then unpacked it
into eax and edx using a move, a right shift, and then another move.
We can combine the second shift and move. The shift will move the
upper 32 bits into the lower 32 bits, and clear the upper 32 bits to
zero. This has the same effect as moving the lower 32 bits post-shift
into another register, since the upper 32 bits will be cleared to zero
based on x86 partial register access semantics.
Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
Reviewed-on: https://gem5-review.googlesource.com/9044
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index b79b6dbe9..04020ef67 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -63,8 +63,7 @@ def macroop RDTSC .serialize_before rdtsc t1 mov rax, rax, t1, dataSize=4 - srli t1, t1, 32, dataSize=8 - mov rdx, rdx, t1, dataSize=4 + srli rdx, t1, 32, dataSize=8 }; def macroop RDTSCP @@ -73,8 +72,7 @@ def macroop RDTSCP mfence rdtsc t1 mov rax, rax, t1, dataSize=4 - srli t1, t1, 32, dataSize=8 - mov rdx, rdx, t1, dataSize=4 + srli rdx, t1, 32, dataSize=8 rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4 }; ''' |