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authorGabe Black <gblack@eecs.umich.edu>2009-08-07 10:13:24 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-07 10:13:24 -0700
commit4f5270f9468cc9959f12206659f84a06c0c2077e (patch)
tree34d85d0d03fd6c93bd92c2056c05e3176729ee97 /src/arch/x86/isa
parent3a55fc5cace5fdf744a891c6d32c4a9d4c10694a (diff)
downloadgem5-4f5270f9468cc9959f12206659f84a06c0c2077e.tar.xz
X86: Implement SHLD.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py46
2 files changed, 48 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 401e02965..c47fb5184 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -820,8 +820,8 @@
Rdx = result.rdx;
}});
0x3: Inst::BT(Ev,Gv);
- 0x4: shld_Ev_Gv_Ib();
- 0x5: shld_Ev_Gv_rCl();
+ 0x4: Inst::SHLD(Ev,Gv,Ib);
+ 0x5: Inst::SHLD(Ev,Gv);
0x6: xbts_and_cmpxchg();
0x7: ibts_and_cmpxchg();
}
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
index caaeca974..d2a579ecb 100644
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
@@ -114,6 +114,52 @@ def macroop SAL_P_R
st t1, seg, riprel, disp
};
+def macroop SHLD_R_R
+{
+ mdbi regm, 0
+ sld reg, reg, rcx, flags=(CF,OF,SF,ZF,PF)
+};
+
+def macroop SHLD_M_R
+{
+ ldst t1, seg, sib, disp
+ mdbi reg, 0
+ sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, sib, disp
+};
+
+def macroop SHLD_P_R
+{
+ rdip t7
+ ldst t1, seg, riprel, disp
+ mdbi reg, 0
+ sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, riprel, disp
+};
+
+def macroop SHLD_R_R_I
+{
+ mdbi regm, 0
+ sldi reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
+};
+
+def macroop SHLD_M_R_I
+{
+ ldst t1, seg, sib, disp
+ mdbi reg, 0
+ sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, sib, disp
+};
+
+def macroop SHLD_P_R_I
+{
+ rdip t7
+ ldst t1, seg, riprel, disp
+ mdbi reg, 0
+ sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, riprel, disp
+};
+
def macroop SHR_R_I
{
srli reg, reg, imm, flags=(CF,OF,SF,ZF,PF)