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authorNilay Vaish <nilay@cs.wisc.edu>2012-09-11 09:25:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2012-09-11 09:25:43 -0500
commit6369df59c85870c0975bc881d7b7d612c9dcf15b (patch)
tree0037bd2955043db5b60c5b967161ed45d30c5d21 /src/arch/x86/isa
parent3700e5448a947197f16e6da07368cbe5fe783fd6 (diff)
downloadgem5-6369df59c85870c0975bc881d7b7d612c9dcf15b.tar.xz
x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since it is not being used any where in the implementation, it creates an unnecessary dependency. Hence, it is being moved to a separate register.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/debug.isa2
-rw-r--r--src/arch/x86/isa/microops/fpop.isa4
-rw-r--r--src/arch/x86/isa/microops/regop.isa64
-rw-r--r--src/arch/x86/isa/microops/seqop.isa4
-rw-r--r--src/arch/x86/isa/microops/specop.isa2
-rw-r--r--src/arch/x86/isa/operands.isa9
6 files changed, 52 insertions, 33 deletions
diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa
index 2d6af8356..b9da9c602 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -142,7 +142,7 @@ let {{
"func": func,
"func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "checkCondition(ccFlagBits | cfofBits | \
- ecfBit | ezfBit, cc)"})
+ dfBit | ecfBit | ezfBit, cc)"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
decoder_output += MicroDebugConstructor.subst(iop)
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 08a74173c..7acbe04ea 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -215,8 +215,8 @@ let {{
spm, SetStatus, dataSize)
code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
- cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
- src2)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \
+ ecfBit | ezfBit, src2)"
class Xorfp(FpOp):
code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index cb1d577d7..a96a552a3 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -438,9 +438,10 @@ let {{
flag_code = '''
//Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit;
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit, ext & ~mask,
- result, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
+ ext & ~mask, result, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
//If a logic microop wants to set these, it wants to set them to 0.
@@ -451,29 +452,32 @@ let {{
class FlagRegOp(RegOp):
abstract = True
flag_code = '''
- uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
- ezfBit, ext, result, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, ext, result, psrc1, op2);
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
class SubRegOp(RegOp):
abstract = True
flag_code = '''
- uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
- ezfBit, ext, result, psrc1, ~op2, true);
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, ext, result, psrc1,
+ ~op2, true);
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
class CondRegOp(RegOp):
abstract = True
- cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
- ext)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \
+ ezfBit, ext)"
cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
class RdRegOp(RegOp):
@@ -732,9 +736,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -774,9 +779,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -815,9 +821,10 @@ let {{
}
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -856,9 +863,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -901,9 +909,10 @@ let {{
}
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -943,9 +952,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -990,9 +1000,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1047,9 +1058,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1110,9 +1122,10 @@ let {{
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1130,6 +1143,7 @@ let {{
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
@@ -1140,6 +1154,7 @@ let {{
// Get only the user flags
ccFlagBits = newFlags & ccFlagMask;
+ dfBit = newFlags & DFBit;
cfofBits = newFlags & cfofMask;
ecfBit = 0;
ezfBit = 0;
@@ -1152,22 +1167,25 @@ let {{
code = 'DestReg = NRIP - CSBase;'
class Ruflags(RdRegOp):
- code = 'DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit;'
+ code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;'
class Rflags(RdRegOp):
code = '''
- DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit | nccFlagBits;
+ DestReg = ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit | nccFlagBits;
'''
class Ruflag(RegOp):
code = '''
- int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+ int flag = bits(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, imm8);
DestReg = merge(DestReg, flag, dataSize);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
big_code = '''
- int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+ int flag = bits(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, imm8);
DestReg = flag & mask(dataSize * 8);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
@@ -1180,7 +1198,7 @@ let {{
class Rflag(RegOp):
code = '''
MiscReg flagMask = 0x3F7FDD5;
- MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+ MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
@@ -1190,7 +1208,7 @@ let {{
big_code = '''
MiscReg flagMask = 0x3F7FDD5;
- MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+ MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index e3b251162..d60ddced7 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -172,7 +172,7 @@ let {{
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
{"code": "nuIP = target;",
"else_code": "nuIP = nuIP;",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
"cond_control_flag_init": "flags[IsCondControl] = true"})
exec_output += SeqOpExecute.subst(iop)
@@ -190,7 +190,7 @@ let {{
iop = InstObjParams("eret", "EretFlags", "SeqOpBase",
{"code": "", "else_code": "",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
"cond_control_flag_init": ""})
exec_output += SeqOpExecute.subst(iop)
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index 8092b28b9..2f6bbd58d 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -181,7 +181,7 @@ let {{
iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
{"code": "",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)"})
exec_output = MicroFaultExecute.subst(iop)
header_output = MicroFaultDeclare.subst(iop)
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 8e2ae7fd4..e0cd2d628 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -120,12 +120,13 @@ def operands {{
# nccFlagBits version holds the rest.
'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
- 'ecfBit': intReg('INTREG_PSEUDO(2)', 62),
- 'ezfBit': intReg('INTREG_PSEUDO(3)', 63),
+ 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
+ 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
+ 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
# These register should needs to be more protected so that later
# instructions don't map their indexes with an old value.
- 'nccFlagBits': controlReg('MISCREG_RFLAGS', 64),
- 'TOP': controlReg('MISCREG_X87_TOP', 65, ctype='ub'),
+ 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
+ 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
# The segment base as used by memory instructions.
'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 10:14:29 +0000