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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 20:22:56 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 20:22:56 -0700
commit75528a497c1980a55256e068473da8e0d684c8ab (patch)
treee536e2844b882e979fea916470c1b06d6ba7a84a /src/arch/x86/isa
parent90dc1abd0b95efc37f0bb12ed1dddd22e0d5d914 (diff)
downloadgem5-75528a497c1980a55256e068473da8e0d684c8ab.tar.xz
X86: Implement a mask move microop.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index bef661848..83962b0f2 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -347,6 +347,24 @@ let {{
DestReg = DestReg | result;
'''
+ class Maskmov(MediaOp):
+ code = '''
+ assert(srcSize == destSize);
+ int size = srcSize;
+ int sizeBits = size * 8;
+ int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size);
+ uint64_t result = FpDestReg.uqw;
+
+ for (int i = 0; i < items; i++) {
+ int hiIndex = (i + 1) * sizeBits - 1;
+ int loIndex = (i + 0) * sizeBits;
+ uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
+ if (bits(FpSrcReg2.uqw, hiIndex))
+ result = insertBits(result, hiIndex, loIndex, arg1Bits);
+ }
+ FpDestReg.uqw = result;
+ '''
+
class Unpack(MediaOp):
code = '''
assert(srcSize == destSize);